01016pam a2200301 c 4500001001300000005001500013007000300028008004100031020003400072023001800106049002800124052001700152056001300169082001700182245004200199260004500241300003000286500006300316504002500379650004600404650004700450700006100497700004400558880004500602880002800647880002800675950001100703KMO20182192920180726105750ta180213s2018    ulka          000   kor    a9788998753191g93560:c\15000  aCIP20180054270 lEM6960270lEM6960271c201a569.3b18-14  a569.32601a621.381522300aVHDL /d저자: 강희훈,e이영종  6880-01a서울 :b지식더하기,c2018  a164 p. :b삽화 ;c26 cm  aVHDL은 "VHSIC Hardware Description Language"의 약어임  a참고문헌: p. 161 8a디지털 회로[--回路]0KSH1998027666 8a회로 설계[回路設計]0KSH20010156701 6880-02a강희훈,g姜熙勳,d1971-0KAC2014115824aut1 6880-03a이영종,d1957-0KAC201825996  6260-01/(BaSeoul :bJisik Deohagi,c20181 6700-02/(BaGang, Huihun1 6700-03/(BaI, Yeongjong0 b\15000