00700nam a2200205 k 4500001001300000005001500013008004100028020003100069035001800100049002800118052001500146056001300161082001700174245008300191260003300274300002600307653009700333700005300430950001100483KMO20030324320180528114417030225s2002 ulka 000 kor  a8955000553g93530:c\10000 aUB200300173750 lEM2734008lEM2734009c201a569.3b3-7 a569.3240 a621.381522120a(Maxplus II와 VHDL을 이용한)디지털 회로설계 실습/d이행우 著 a서울:b과학기술,c2002 a172p.:b삽도;c26cm aMAXPLUSaMAXPLUSIIaVHDLa디지털a회로설계a디지털회로설계a회로설계실습1 a이행우,g李倖雨,d1960-0KAC2018292704aut0 b\10000